VHF harmonic impedance tuner

ABSTRACT

An impedance synthesis method for fundamental and harmonic frequencies using multi section tuners, because of the huge amount of possible tuning permutations, employs a search strategy based on the minimization of an ERROR FUNCTION (EF), in two steps: in a first step a coarse calibration grid is generated and the raw area is found which allows an approximate solution to the tuning task at the fundamental frequency; then a fine impedance grid is generated around the first solution using calibrated and interpolated points at all harmonic frequencies; a second search step, using the same EF, then allows fine tuning. Among the several, numerically found solutions, the most reliable one is selected based on a sensitivity criterion, which calculates the impedance change for a possible small error in repeatability of each tuning element and selects the one with the lowest sensitivity to element setting errors.

PRIORITY CLAIM

This application is a continuation of U.S. Non-Provisional application Ser. No. 13/180,796, filed on Jul. 12, 2011, and titled VHF HARMONIC IMPEDANCE TUNER, which is incorporated herein by reference in its entirety.

CROSS-REFERENCE TO RELATED ARTICLES

-   [1] Tsironis, U.S. Pat. No. 7,646,267, Low frequency     electro-mechanical impedance tuner. -   [2] Adamian et al. U.S. Pat. No. 5,034,708, Programmable broad and     electronic tuner. -   [3] Tsironis, U.S. Pat. No. 7,646,268, Low frequency harmonic load     pull tuner and method. -   [4] Tsironis, U.S. Pat. No. 6,297,649, Harmonic rejection load     tuner, FIG. 6. -   [5] Simplex algorithm,     http://en.wikipedia.org/wiki/Simplexalgorithm. -   [6] A Load Pull System with Harmonic Tuning, ATN Microwave Inc.,     Microwave Journal, March 1996. -   [7] MPT, a Universal Multi-Purpose Tuner, Focus Microwaves Inc.,     Product Note 79, October 2004. -   [8] iLFT-028009 Low Frequency Tuner, Data Sheet,     www:focus-microwaves.com. -   [9] Application Notes: Tuning Varactors, Aeroflex Microelectronics     Solutions, Revision Date Apr. 13, 2009,     www.aeroflex.com/ams/Metelics/pdfiles/ANTV.pdf.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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REFERENCE TO SEQUENCE LISTING, A TABLE, OR A COMPUTER PROGRAM LISTING COMPACT DISC APPENDIX

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BACKGROUND OF THE INVENTION

This invention relates to load pull testing of VHF frequency transistors and amplifiers, at frequencies typically between 10 MHz and 150 MHz, under high power operating conditions, using automatic impedance tuners in order to synthesize impedances at the input and output of the test devices (DUT) at the fundamental and various harmonic frequencies.

Load Pull is a measurement technique, in which the source or load impedance of a DUT (typically a power RF transistor) is changed systematically using pre-calibrated impedance tuners. This technique is popular at frequencies in the GHz frequency range but unknown in the VHF frequency range, especially below 100 MHz.

Accurate design of high power amplifiers, oscillators and other active components used in various communication systems requires accurate knowledge of the active device's (RF transistor's) characteristics under high power operation conditions. In such circuits, it is insufficient and inaccurate to describe transistors, operating at high power in their highly non-linear regions close to saturation, using analytical or numerical models only. Instead the transistors need to be characterized using specialized test setups under the actual operating conditions.

A popular method for testing and characterizing such components (transistors) under high power operation conditions has been developed at much higher frequencies in the GHz frequency range, as “load pull” and “source pull”. Load pull or source pull are measurement techniques employing RF impedance tuners and other RF test equipment, such as RF signal sources and RF power meters. Since transistors are typically used close to power saturation conditions in high efficiency amplifiers, their internal nonlinearities create harmonic frequency components. Those components, if not presented with the appropriate RF impedance will degrade the performance of the amplifier. In order to determine the proper RF impedance a Harmonic Load Pull system is required. In such a system certain components such as frequency discriminators (Diplexers or Triplexers) are used, whose task is to separate the harmonic components generated by the DUT into different paths, where they can be treated separately (FIG. 1). Harmonic impedance tuners [4] are also used in order to manipulate the harmonic microwave impedances presented to and under which the Device under Test (DUT, amplifier or transistor) is tested (FIG. 2).

FIG. 1 shows a setup using a frequency diplexer or triplexer in order to create three independent frequency paths, loaded each with a wideband tuner. This concept of harmonic tuning is well known in the literature and is valid for all frequencies for which appropriate components such as tuners and diplexers/triplexers exist. Because of lack of such components harmonic load pull test systems are not known for frequencies below 100 MHz. This, on the other hand is due to the difficulty in manufacturing such components because of their required size to handle low frequencies and large wavelengths.

A simpler solution for a harmonic load pull test system will use a single multi-harmonic tuner [7], i.e. a tuner which allows independent tuning at harmonic frequencies without using frequency discriminators, such as diplexers and triplexers. Such a setup is shown in FIG. 2.

DESCRIPTION OF PRIOR ART

Electro-mechanical low frequency tuners have been disclosed in [1]; they are made using variable rotary shunt capacitors (C1, C2, C3 in FIG. 3 and FIG. 4) and fixed lengths of coaxial cable between them (L1, L2, L3 in FIG. 3). The capacitors are driven by electrical motors, best suited are stepper motors, because they define precisely the angle of the rotating capacitor blades. By using capacitors of various maximum values and varying each of them between its minimum and maximum values the reflection factor r (FIG. 3) describes an arc on the Smith Chart (FIG. 5). The various sets of traces (1, 2 and 3) are created when various lengths of cable (L1, L2, and L3 in FIG. 3) are inserted between the capacitors. The various traces within each set (4, 5 and 6) are created by the same capacitor at different frequencies. As the frequency changes those shapes change as well, since both the actual impedance value of the capacitors change with frequency as do the electrical lengths of the cables. The result is a quasi total reflection factor coverage for each specific frequency (FIG. 6) as a function of the settings of the shunt capacitors. In this specific case (FIG. 6) each of the three capacitors has been adjusted to 10 values and the permutation of all three yields 1000 tuner settings, as shown. The effect is similar at the harmonic frequencies as well, as marked by 2Fo and 3Fo in FIG. 6.

Harmonic VHF load pull impedance tuners have been disclosed in [2]; they comprise three variable shunt capacitors connected between them with variable phase shifters/line stretchers (FIG. 7) and are able to create and adjust reflection factors at a fundamental frequency (Fo) and one or two harmonic frequencies (2Fo, 3Fo) independently. In this configuration the line stretchers must be at least Lambda/2 long at le lowest frequency of operation; for example at F=10 MHz this is 15 meters. It is therefore obvious that this configuration is not suitable for such low frequencies.

The alternative solution described here is a harmonic load pull setup, which uses either readily available or reasonably made operational components in the 10 MHz to 250 MHz frequency range, which are combined in such a way as to allow a harmonic tuner to be assembled, calibrated and operated efficiently.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention and its mode of operation will be more clearly understood from the following detailed description when read with the appended drawings in which:

FIG. 1 depicts prior art, a GHz frequency-range harmonic load pull system.

FIG. 2 depicts prior art, a GHz frequency range harmonic load pull system using an harmonic tuner.

FIG. 3 depicts prior art, a low frequency impedance tuner.

FIG. 4 depicts prior art, variable air capacitors controlled by stepper motors.

FIG. 5 depicts prior art, the reflection factor as a function of variable shunt capacitances and lengths of cable.

FIG. 6 depicts prior art, distribution of 1000 calibration points of VHF tuner shown at Fo=40 MHz.

FIG. 7 depicts prior art, low frequency harmonic tuner.

FIG. 8 depicts a VHF tuner for 2 frequency/harmonic tuning.

FIG. 9 depicts a VHF tuner for 3 frequency/harmonic tuning.

FIG. 10 depicts Smith chart coverage (%) of 3 capacitor tuning sections.

FIG. 11 depicts the definition of Smith chart coverage (%).

FIG. 12 depicts calibrating the Vector Network Analyzer (VNA).

FIG. 13 depicts setup for calibrating the VHF harmonic tuner.

FIG. 14 depicts Load pull measurement setup using a VHF harmonic load tuner.

FIG. 15 depicts Load and Source pull measurement setup using VHF harmonic tuners.

DETAILED DESCRIPTION OF THE INVENTION

A new configuration for a VHF harmonic tuner is described using the general concept of low frequency three-capacitor tuners [1] and but a different approach than low frequency harmonic tuners with three independent tuning sections, each section comprising a variable shunt capacitor and a phase shifter/line stretcher [3]. The tuner in [3] has an important shortcoming: because it operates at low MHz frequencies it requires long phase shifters/line stretchers of at least one half of a wavelength each (1.5 meters at 100 MHz and 15 meters at 10 MHz), which are •difficult to manufacture; beyond the hardware itself, computerized control and appropriate calibration and tuning solution search algorithms are required to make the harmonic/multi-frequency tuning possible.

The present apparatus uses three or more tuning sections in order to generate the large amount of combined impedance states that will allow simultaneous and independent tuning at multiple frequencies. Assuming a number of 20 capacitor settings for each capacitor in each of the tuning sections, the total number of combinations of one tuning section, comprising 3 capacitors, is 20³=8,000 states for each frequency, harmonic or not. A cascade of two such tuning sections will generate a total of 8,000²=64,000,000 states; and a cascade of three such tuning sections will generate a total of 8,000³=512,000,000,000 states, for each frequency. If it can be arranged that said impedance states are distributed over most of the area of the Smith chart at each of the frequencies under consideration (harmonic or not) (7) i.e. frequencies F1, F2, F3 in FIG. 10, then it is statistically certain that there will be capacitor value combinations allowing independent impedance synthesis at those said frequencies. This is valid as well for three tuning sections as for two tuning sections [6]. If said coverage is not obtained (8) as shown for frequencies F4, FS, F6 in FIG. 10, then independent multi-frequency (harmonic) tuning will not be possible over the entire Smith chart.

FIG. 11 shows a definition of “Smith chart coverage”, as used in this invention. It is an efficient method for asserting the capacity of a multi-section tuner to generate arbitrary independent impedances at various (harmonic or not) frequencies. Said tuning capacity decreases with the corresponding Smith chart coverage.

Variable capacitors are available in many forms, either mechanical (rotary vane capacitors) or electronic form (Varactors); variable mechanical capacitors can be controlled by connecting the axis of the moving section to a remotely controlled stepping motor (FIG. 4). Typical stepping motors tum 0.9 to 1.8° per step; this means it takes 200 to 400 steps per 360° revolution; typical mechanically adjustable rotary vane capacitors, as shown in FIG. 4, allow for a 180° tum between minimum and maximum capacitance value. This means that, without any special arrangements each capacitor can be set to between 100 and 200 distinct positions driven by an ordinary stepping motor and associated control software. This, compared with the 10 to 20 states mentioned before, means an increase in available tuner states by a factor between 10 and 20 for each tuning section, or between 10³=1,000 and 20³=8,000 for the three cascaded sections. This factor is to be multiplied by the 512*10⁹ already tunable points.

The harmonic tuner needs to be calibrated before using it in a load pull setup. Calibration consists in using a network analyzer (VNA, FIG. 12), which has been calibrated separately before, measuring the scattering parameters (s-parameters) of the tuner between its test port and idle port for different states (=motor positions, corresponding to capacitor values), by retrieving the data through the instrument control link by the control computer and saving on disk in sets of s-parameters and associated motor positions, called calibration files. This data are then recalled and used to reproduce the impedance states to be presented to the DUT during testing. The network analyzer must be calibrated before the above operation, using known methods and calibration standards at the test port and idle port reference planes of the tuner.

Since the harmonic tuner has a total of nine independent variable capacitors, which can each be set at a number of states, it is obvious that we have to deal with a very large permutation problem. Assuming a simple scenario of each variable capacitor being set to 20 different values, then the total number of combined states to measure amounts to 20⁹=5.12*10¹¹. Typical motor setting and instrument data retrieval time from the VNA being at an average of at least 1 second, the calibration procedure of all tuner settings at one set of frequencies Fo, 2Fo, 3Fo would amount to 16,460 years. In other words, the tuner cannot be calibrated and used this way.

However, it is possible to calibrate the tuner in short time using a “de-embedding” technique. This consists in measuring the s-parameters of the overall tuner twoport between the test port and the idle port for each one-capacitor tuning element, set individually at a number of states (typically 20 or more) and cascading the result of each capacitor, except the first one, with the inverses-parameter matrix of said initialized tuner two-port (de-embedding), measured under the condition where all capacitors are initialized (set to the lowest capacitance possible). The s-parameter data of each element's calibration, comprising s-parameters associated with the, typically 20, motor positions, are saved in a “calfile” to be processed later. This method is referred to hereby as “de-embedding calibration” (DE-CAL). In that case the total settings to be measured are 9×20=180 and if each measurement event takes 1 second the total measurement time is 3 minutes. Permutations of the s-parameters saved in the calfiles are subsequently generated in the computer memory in a few seconds.

If the overall tuner is made as a dis-connectable cascade of three “three-capacitor” tuner sections then a possible alternative to this calibration method is to disassemble the cascaded tuner, measure the s-parameters of each section separately, using the same “de-embedding calibration” technique for each section and save the data on the hard-disk. Then proceed as outlined below and cascade all data into a combination calibration matrix. This method will work for tuners which can easily be divided in distinct tuning sections and the internal ports between tuning sections can be made accessible; however it is a •cumbersome method and the disassembling and re-assembling of RF connections usually creates inaccuracies, RF repeatability problems and measurement errors, it is therefore not a preferred calibration method.

The “de-embedding calibration” technique outlined before consists in collecting s-parameter data through digital cable (15) from the network analyzer (14) into the control computer (17) and numerically processing them (FIG. 12). However the network analyzer (VNA) itself (14) has an internal computer and processing capacity. What the VNA does, in fact, • is detect signals at the ends of the RF cables (test ports, Port 1, Port 2) and cascade them with the “error terms” or an “error two-port” between the test ports and its internal signal detectors. This way the measurement reference can be shifted from the signal detectors themselves to the cable test ports (13, 16). In order to calibrate a multi-element tuner this capacity of the VNA can be used to replace the first step of the “de-embedding” calibration (DE-CAL) outlined before. In this case the VNA is calibrated in two steps: in a first step (FIG. 12 a) the VNA is calibrated using only the RF cables at the test ports of said cables. The “error terms” are saved in the VNA's memory as CALSET 1. In a second step the test port of the initialized tuner is connected to the end of the RF cable (Port 1) and the idle port of said tuner is forming a new test port (FIG. 12 b); the VNA is then calibrated under the same settings and frequencies as before at this new •reference plane (16). The new “error terms” are saved in the VNA's memory as CALSET 2. The new “de-embedding” calibration of the VNA, named here “VNA de-embedding calibration” (VNA-DE-CAL) is then used to calibrate the multi-element tuner.

The multi-element tuner comprising N tuning elements (i=1 to N) is calibrated using the VNA-DE-CAL of the VNA as follows: The tuner is connected between the test ports of the VNA cables (FIG. 13). In a first step CALSET 1 is loaded into the VNA active memory and used to correct the measurements; all tuning elements of said tuner are initialized and only element 1 (the element closest to the tuner's test port) is being set at various positions (settings) and the tuner's s-parameters are measured for all settings of element 1, all other elements being initialized, and saved in a file (calfile 1). In a second step CALSET 2 is loaded into the VNA's active memory and used to measure the s-parameters of the other tuning elements 2 to N, one by one; during this measurement only one element is moving and all others are initialized; the s-parameter data of each element (i) are saved in a corresponding file (calfile i). Permutations of the s-parameters saved in the calfiles i, for i=1 to N, are then made in computer memory in a few seconds.

All that has been outlined in the previous paragraphs for the case of a harmonic tuner with nine motors and nine associated variable capacitors (which corresponds to three independent tuning-sections) is directly applicable to the case of a two tuning-sections tuner (six motors and capacitors) or even the more complex four tuning-sections (twelve motors and capacitors). In this last case, of course, computer memory and speed may be a limitation, since the necessary permutations are huge (the equivalent of 20¹²=4.1*10¹⁵). Techniques and search strategies have been developed though not to use all available data, but to proceed in two steps, i.e. selecting a coarse permutation net first, such as use only 5 or 7 capacitor settings between the minimum and maximum capacitor values (=motor positions), and search first inside this grid, until the impedance search reveals the closest capacitor values, where a solution of the tuning problem exists, and then create permutations in this capacitor value area only, and subsequently proceed with a finer search.

In the case of a 12 capacitor tuner, calibrated at 21 capacitor/motor settings (1 to 21) a two step search approach is used: In a first step we create permutations for settings 1-6-11-16 and 21=5 settings. The permutations matrix includes 5¹²=2.44*10⁸ combinations, which is a number of data points that can be processed rapidly with a fast duo-core or quad-core computer processor. The first search will yield a set of solutions in the vicinity of, for example, settings “Si” for each of the 12 capacitors (i=1-12). Then, in a second step, we create permutations for the capacitor settings Si−2, Si−1, Si, Si+1, Si+2, for each capacitor. This again amounts to 5¹²=2.44*10⁸ combinations and the solution obtained will be as accurate as could be expected from a 21-settings calibration (which would require a search in a data block containing 21¹²=7.36*10¹⁵ data points). This reduces the search time by a factor of approximately 10,000,000.

Since the VHF tuner of this invention can be considered as a cascade of shunt capacitors Ci with series inductors Li the overall impedance of said tuner can be calculated as a series of parallel-series networks as follows: Y1=jωC1; Z1=1/Y1+ωL1; Y2=1/Z1+jωC2; Z2=1/Y2+jωL2 etc. or in a general form: Zn=1/Yn+jω Ln (eq 1); Yn=1/Zn−1+jωCn (eq 2).

The differential δYi of any Yi as a function of the change in a capacitor Ci can be calculated as: δYi=1/Zi−1+jωCi and the differential δZi of any Zi can be calculated as δZi=−1/(Yi²*Zi−1)*jωCi; Even though analytic expressions of such impedances of a cascade of shunt capacitors and series inductors will involve stacked multiplications and divisions by complex numbers, the computer calculations are straight forward, because they are executed in a numerical step-by-step manner and not at once. Using above general equations 1 and 2 said changes can be calculated immediately for any combination of capacitor changes, always starting with the first capacitor. If we consider the whole tuner being a series of Zi, then the total impedance Zt seen into the test port of the tuner is: Zt=ΣZi+50 ω (eq 3); we add 50 ω, because s-parameter calculation imposes such a termination, if we intend to convert Z-parameters into s-parameters using the relation: S11=Γ=(Z−Zo)/(Z+Zo); from (eq 3), we can calculate the interpolated or extrapolated value of any impedance Zi by simply using: Zt′=Zt+dZi/dCi*δCi (eq 4); From (eq 4) then we can calculate S11′ easily.

Harmonic tuning is the capacity of a tuner to synthesize, independently, user defined impedances at two or more harmonic frequencies at the same time, if there are no frequency separators, such as filters or diplexers/triplexers (FIG. 1), in which case each harmonic spectrum component is treated in a different signal path, the impedance tuner must synthesize a number of different impedances at different frequencies simultaneously; this is a network design task, but with only limited building blocks (in this case variable capacitors). We obviously deal here with a network of multiple resonances; rational equations describing such a network are, in practice, unsolvable; the most efficient and practical way of handling the requirements of synthesizing simultaneously two or more impedances at two or more frequencies is to use an appropriate numeric trial-and-error search algorithm, which samples systematically through the billions of possible tuner settings, as described before, and finds possible tuner configurations for the requested two or more harmonic impedances (tuning).

It has to be mentioned here that the solutions the search algorithm determines are not exact. The way the search algorithm operates, is to search for “nearby” solutions by using an ERROR function. An error function is the sum of differences between the target impedances Zt and an obtained value Zc for one, two or three harmonic frequencies. Higher harmonic frequencies can also be included.

The Error Function used for this optimization task is: EF=Σ{┌t(Fi)−└c(Fi)}, where Fi are various/harmonic frequencies, └t are target reflection factors (impedances) and └c are obtained solutions of the harmonic tuning process. The sum Σ is built over (i) which is the number of (harmonic) frequencies and the variables are the motor positions which set the capacitor values, and which are associated with s-parameters (or Z parameters) in the calfiles. When the Error Function EF reaches a minimum value, we have a solution. As in many multi-parameter optimization problems we often get several local minima and the search algorithm has to decide whether to • continue searching by changing the starting values of the search, or stop and declare a solution found. Several optimum search algorithms applicable here are known in the literature [5], [8]. We used a gradient and a simplex optimization method alternatively.

The harmonic load pull tuner is used in a load pull setup, shown in FIG. 14. It comprises, in its simplest configuration, a signal source, a driver amplifier, a DUT fixture, the DUT itself, the harmonic tuner and a power meter. All instruments are remotely programmable by digital interface. Such digital interface are GPIB, serial, USB or TCPIIP are also possible. The tuner and the instruments are all remotely controlled, set and read from a system control computer, which runs appropriate software; the software processes tuner calibration and interpolation data, calculates tuner positions and sets the motors and once the impedance conditions are set, it sets the input signal power required and reads the power meter. The measured results are saved in load pull data files, which can then be plotted using contouring software or can be processed otherwise. Additional instruments, such as a source tuner, a second signal source, a remote power supply and a spectrum analyzer can be added to the setup, for additional testing; although this has been known in the art it shall not impede on the originality of the present invention.

The interpolation routines used in this preferred embodiment, as well as the calibration techniques used are deemed to be the most appropriate for the purpose of harmonic tuning; however different methods can be used for this purpose, but this shall not infer with the innovation and basic idea of the apparatus and its operation described here.

The present embodiment of this invention can easily be adapted to use other types of mechanically adjustable variable capacitors, or electrically adjustable ones, such as Varactor or high frequency Trimmer Capacitor based [9, 10], which cover higher frequencies, above 200 MHz; this shall not limit the basic idea and the overall scope of the present invention, of using a series of six or more remotely adjustable variable capacitors joined with transmission lines as building blocks of a harmonic load pull tuner. 

What I claim is:
 1. A harmonic impedance tuning method (simultaneous synthesis of a set of target impedances at a multitude of harmonic frequencies) for calibrated multi-tuning element impedance tuners comprises the following steps: a) search for an approximate tuning solution (tuner state) at the fundamental frequency (fo), in a coarse calibration grid, b) creation of a fine interpolation grid surrounding the solution found in (a), c) search for tuning solutions at all harmonic frequencies (fo, 2fo, 3fo, . . . ) using the fine grid created in (b), d) select, among the solutions found in (c) the solution with the lowest tuning sensitivity, e) set said tuning elements of said tuner to the solution found in (d).
 2. A tuning method as in claim 1, whereby said coarse calibration grid is generated by selecting a fraction of calibrated settings for each tuning element, equally distributed over its whole variation range, and calculating the reflection factors for all permutations for the selected settings of all tuning elements, at the fundamental frequency (fo).
 3. A tuning method as in claim 2, whereby a numeric search routine selects the calibration point (P0) in said coarse grid, corresponding to a minimum tuning error function (EF1), said EF1 being defined as the vector difference between target and calibrated reflection factors for said fundamental frequency, and saving said coarse calibration point (P0) in memory.
 4. A harmonic tuning method as in claim 3, whereby a fine calibration grid is created in an area around said coarse calibration point (P0) using numerical interpolation, said fine grid area covering typically 1/100 of the Smith chart surface, said fine grid comprising reflection factors of all permutations of all tuning elements at the fundamental and all harmonic frequencies, and a numerical search is conducted inside said fine calibration grid for a minimum error function (EF2), said search using, alternatively, simplex and gradient search algorithms, and whereby a multitude of tuner states P1, P2, P3 . . . are selected which satisfy the condition EF2<TE, whereby TE is a pre-defined allowable tuning error.
 5. A harmonic tuning method as in claim 4, whereby said ERROR FUNCTION (EF2) comprises the weighed sum of the absolute value of the vector differences between the target reflection factors and synthesized reflection factors corresponding to the associated target and synthesized impedances at all calibrated harmonic frequencies, as follows: ERROR FUNCTION=SUM{W(Nfo)*|Gamma_Target(Nfo)−Gamma_Tuned(Nfo)|}, whereby SUM is the sum over all values of N, and whereby fo is the fundamental frequency, and whereby N is the harmonic frequency index 1, 2, 3 . . . , at which said tuner has been calibrated and target impedances have been defined, and whereby W(Nfo) is a weight factor associated with each frequency, and whereby Gamma_Target(Nfo) is the reflection factor corresponding to the target impedance Z_Target at said harmonic frequency Nfo, to be generated by said tuner, and Gamma_Tuned(Nfo) is the reflection factor corresponding to the tuned impedance Z_Tuned at said harmonic frequency Nfo, actually generated by said tuner.
 6. A harmonic tuning method, whereby a search routine determines the final tuning solution in two steps: a) calculation of tuning sensitivity (TS) for each tuner state P1, P2, P3 . . . , as determined in claim 4, said tuner states corresponding to reflection factors Gamma1, Gamma2, Gamma3 . . . , b) select tuner state PX for which said tuning sensitivity is minimum, whereby said tuning sensitivity (TS) is defined as the maximum weighed sum of reflection factor changes when each tuning element (TEi) is changing by a small amount ±deltaTEi, and whereby said weighing factors are selected individually for each frequency.
 7. A harmonic tuning routine, whereby said tuning elements of said impedance tuner are placed at the states corresponding to the overall tuning solution PX, as determined in claim
 6. 